Generally, the conventional flip chip bumps have vertical or nearly vertical sidewalls and are connected to an underlying trace (such as on a substrate, a printed circuit board, an interposer, another chip, or the like) using a solder reflow process.
The solder joint method forms intermetallic compounds (IMCs) between the metal-solder interface. The IMCs may cause higher electrical resistivity (contact resistance). The higher electrical resistivity leads to increased electromigration, which further increases the contact resistance. In addition, with a small area under bump metallurgy (UBM), the solder/metal electromigration issue may be of greater concern.
As device packaging dimensions shrink, the smaller distance between the bump and an adjacent trace may lead to undesirable bridging during reflow. In addition, as device packaging dimensions shrink interconnect bump sizes also shrink. The reduction in bump size has led to an increase in interconnect resistance and capacitance (RC) that is the cause of signal transmission delay (RC delay). Smaller bump sizes also increases the risk of extremely low-k (ELK) dielectric delamination.
Corresponding numerals and symbols in the different figures generally refer to corresponding parts unless otherwise indicated. The figures are drawn to clearly illustrate the relevant aspects of the embodiments and are not necessarily drawn to scale.